The disclosed device relates to a magnetic random access memory (MRAM), and in particular, to an improved MRAM having a higher speed than static random access memory (SRAM),integration density comparable to dynamic random access memory (DRAM), and properties of nonvolatile memory such as a flash memory.
MRAMs using a ferromagnetic material have been developed as a next generation memory device. The MRAM is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films, and sensing current variations according to a magnetization direction of the respective thin film. The MRAM has high speed, low power consumption and allows high integration density due to the special properties of the magnetic thin film, and performs nonvolatile memory operations such as a flash memory.
The MRAM is utilized as a memory device by using giant magneto-resistive (GMR) materials or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission. MRAMs using GMR materials operate on the phenomenon that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer therebetween to implement a GMR magnetic memory device. MRAMs using SPMT utilize the phenomenon that a larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween to implement a magnetic permeable junction memory device. However, the MRAM research is still in its early stage, and mostly concentrated on the formation of multi-layer magnetic thin films. There is less concentration on researching unit cell structures and peripheral sensing circuits.
FIGS. 1 through 3 are cross-sectional diagrams illustrating respectively first, second and third examples of a conventional MRAM. In these examples, the MRAM includes one diode and one MTJ cell. FIG. 1 is a cross-sectional diagram illustrating a first example of the conventional MRAM as described in Gallagher, et al., U.S. Pat. No. 5,640,343. Referring to FIG. 1, the MRAM includes a semiconductor substrate 11 having a word line 13 formed thereon. A diode 19, having N/P type impurity layers 15 (N-type) and 17 (P-type), is provided on the word line 13. A stacked structure including a connection layer 21, a magnetic tunnel junction (MTJ) cell 23 and a bit line 25 is formed on the diode 19.
FIG. 2 is a cross-sectional diagram illustrating a second example of a conventional MRAM as described in Scheuerlein, U.S. Pat. No. 6,097,625. Referring to FIG. 2, the MRAM includes trench isolators 33 formed in a semiconductor substrate, and a diode 39. The diode 39 includes an N-type impurity layer 35 formed by implanting a highly-doped N-type impurity into the semiconductor substrate 31 between the trench isolators 33, and a P-type impurity layer 37 formed by implanting a highly-doped P-type impurity into one side of the N-type impurity layer 35. A first interlayer insulating film 41 is formed on the semiconductor substrate 31. A first contact plug 43 is connected to the N-type impurity layer 35 through the first interlayer insulating film 41. A word line 45 is connected to the first contact plug 43. A second interlayer insulating film 47 planarizes the top surface of the resultant structure. A second contact plug 49 is connected to the P-type impurity layer 37 through openings in the first and second interlayer insulating films 41, 47. A connection layer 51 contacts the second contact plug 49, and a third interlayer insulating film 53 is planarized to expose the connection layer 51. A stacked structure, including an MTJ cell 55 and a third contact plug 57, is formed above the word line 45 on the connection layer 51. A fourth interlayer insulating film 59 is planarized as high as the stacked structure, and a bit line 61 connects to the third contact plug 57. Scheuerlein ""625 also mentions that the MRAM can be formed without using the third contact plug 57.
FIG. 3 is a cross-sectional diagram illustrating a third example of a conventional MRAM also described in Scheuerlein ""625. Referring to FIG. 3, the MRAM includes a semiconductor substrate 71. Trench isolators 73 are formed in the semiconductor substrate 71. An N/P diode 79 having an N-type impurity layer 75 is formed by implanting a highly-doped N-type impurity into the semiconductor substrate 71 between the trench isolators 73, and a P-type impurity layer 77 is formed by implanting a highly-doped P-type impurity into one side of the N-type impurity layer 75. A gate electrode 81 is formed over the semiconductor substrate 71 and a first interlayer insulating film 83 planarizes the top surface of the resultant structure. A first contact plug 85 connects to the N-type impurity layer 75 through an opening in the first interlayer insulating film 83 and a word line 87 connects to the first contact plug 85. A second interlayer insulating film 89 planarizes the top surface of the resultant structure. A second contact plug 91 is connected to the P-type impurity layer 77 through openings in the first and second interlayer insulating films 83, 89. A connection layer 93 contacts the second contact plug 91, and a third interlayer insulating film is planarized to expose the connection layer 93. A stacked structure of an MTJ cell 97 and a third contact plug 99 is formed above the word line 87 on the connection layer 93. A fourth interlayer insulating film 101 is planarized as high as the stacked structure, and a bit line 103 is connected to the third contact plug 99.
The MRAM of FIG. 3 may also be formed without using the third contact plug 99. The addition of the gate electrode 81 improves performance of the diode and allows for higher performance sensing.
FIG. 4 is a circuit diagram as shown in Scheuerlein, U.S. Pat. No. 5,793,697, illustrating the operational principles of an MRAM array having the structures of FIGS. 1 through 3. FIG. 4 illustrates a word line control circuit 111 attached to both ends of a first word line 113, a second word line 115 and a third word line 117. A bit line control circuit 121 is attached to both ends of a first bit line 123, a second bit line 125 and a third bit line 127 crossing the word lines 113, 115, 117. A unit cell having an MTJ cell xe2x80x98bxe2x80x99 and a PN junction diode xe2x80x98cxe2x80x99 is formed at an intersection area of the word lines 113 and the bit line 123.
A magnetic field is generated due to a current IB flowing through the bit lines 123, 125, 127 and a current IW flowing through the word lines 113, 115, 117. A write operation to a selected cell is performed by respectively passing the current IB and the current IW through the word line 113 and bit line 123 of the selected cell.
In addition, a sense current xe2x80x98axe2x80x99 is generated due to a difference between a voltage applied to the bit line of the selected cell and a reference voltage. The sense current xe2x80x98axe2x80x99 flows from the bit line 123 through the MTJ cell xe2x80x98bxe2x80x99 and through the resistance of the diode xe2x80x98cxe2x80x99 to the word line 113. A read operation is executed by sensing variations in the sense current xe2x80x98axe2x80x99.
Because the MRAM described above is formed by using one diode and one MTJ cell, thereby forming a resistance transfer device, only one bit is stored in one cell. This makes it difficult to achieve high integration density for the device.
In accordance with an aspect of the invention, an MRAM is provided which includes a diode and a plurality of resistance transfer devices electrically coupled to the diode.
In accordance with another aspect of the invention, an MRAM is provided which includes a diode, a word line electrically coupled to the diode, a connection layer electrically coupled to the diode and a plurality of connection pairs. Each connection pair comprises a resistance transfer device and a bit line electrically coupled to the resistance transfer device. A first one of the plurality of connection pairs is formed on the connection layer and the bit line of a second one of the plurality of connection pairs is perpendicular to the bit line of the first one of the plurality of connection pairs.
In accordance with yet another aspect of the invention, an MRAM is provided which includes a diode, a first word line electrically coupled to the diode, a second word line electrically coupled to an external power supply, a first connection layer electrically coupled to the diode, a first resistance transfer device formed on the first connection layer above the first word line, a second resistance transfer device formed on the first connection layer above the second word line, and a bit line electrically coupled to the first and second resistance transfer devices.
In accordance with still another aspect of the invention, an MRAM is provided which includes a diode, a first word line electrically coupled to the diode, a first connection layer electrically coupled to the diode, a first resistance transfer device formed on the first connection layer above the first word line, a bist line electrically coupled to the first resistance transfer device, a second resistance transfer device formed on the bit line above the first resistance transfer device, a second connection layer electronically coupled to the first connection layer and the second resistance transfer device, and a second word line formed above the second resistance transfer device.
In accordance with a further aspect of the present invention, an MRAM is provided which includes a diode, a first word line electrically coupled to the diode, a first connection layer electrically coupled to the diode, a first resistance transfer device formed on the first connection layer above the first word line, a first bit line electrically coupled to the first resistance transfer device, a second connection layer electrically coupled to one of the first connection layer and the first bit line; a second word line formed between the second connection layer and the first bit line and above the first resistance transfer device, a second resistance transfer device formed above the second word line on the second connection layer, and a second bit line electrically coupled to the second resistance transfer device.